Encounter Digital Implementation: Tips & Tricks

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  • Wroute in EDI10
  • Floorplan from Virtuoso to Encounter
  • Generating a VERILOG Netlist including FILLCAP cells
  • Generating SDF in MMMC
  • New placement and routing options for 3-metal processes
  • Optimizing Clock Trees for Power
  • Timing DRV Correction for selected nets
  • Avoid modifying of instances during optimization
  • Additional I/O Pins

    Wroute in EDI10
    EDI Version 10 does not include an invocation point in the menus any more. To open the Wroute GUI follwoing command has to be entered in the encounter command line
      encounter> ::Rda_Route::RouteStdCell::create
    This will open the Wroute GUI. If the hitkit environment is used (amsSetup.tcl and enc.tcl script from ams_encounter) a custum menu will be added in Encounter Version 10. It is called hitkit Utilities (is placed on the right end of the menu bar) and it includes the invocation command for the Wroute GUI

    Floorplan from Virtuoso to Encounter

     Instead of using a DEF file to transfer a floorplan from Virtuoso to Encounter the OA view can be directly opend inside Encounter. Boundary, Pins and Blockage elements are then transfered to Encounter. BUT the properties of these elements have to different now (compared to the DEF interface). The best way is to create the floorplan in Virtuoso using following commands:
    - Boundary: Create -> P&R Objects -> P&R Boundary
    - Blockage: Create -> P&R Objects -> Blockage (use F3 to select layers)
    - Pins: Create -> Pin (on layer METx-pin)
       Pin label: should be placed on layer METx-pin also

  • Generate a VERILOG Netlist including FILLERCAP
    To write a Verilog Netlist that includes FILLER cells (with decoupling caps - that have to be in the LVS netlist) use following command:

    saveNetlist filename -excludeLeafCell -includePhysicalInst \    
    -excludeCellInst {FILLCELLX1 FILLCELLX2 FILLCELLX4 FILLCELLX8 FILLCELLX16 FILLCELLX32 ENDCAPR ENDCAPL }

    Modify the celllist according to the library you use
      -excludeLeafCells - avoids writing a module for any standard cell 
      -includePhysicalInst - writes all layout cells into the netlist 
      -excludeCellInst - list of cellnames that should not be included in the netlist (FILL cells without coupling caps, ENDCAP cells,....)

    Generate SDF in MMMC

    Cadence recommends following steps to generate SDFs:

     
    set_analysis_view -setup {func_max func_typ func_min } -hold {func_max func_typ func_min}
     
    timeDesign -signOff -expandedViews -timingDebugReport -outDir REPORTS
    timeDesign -signOff -expandedViews -timingDebugReport -hold -outDir REPORTS
     
    write_sdf -version 3.0 -prec 3 -edges check_edge -force_calculation -view func_max -typ_view func_max ies2_digital_v1_max.sdf
    write_sdf -version 3.0 -prec 3 -edges check_edge -force_calculation -view func_typ -typ_view func_typ ies2_digital_v1_typ.sdf
    write_sdf -version 3.0 -prec 3 -edges check_edge -force_calculation -view func_min -typ_view func_min ies2_digital_v1_min.sdf
     
    The disadvantage with this flow is, that for this kind of  timing analysis (3 corners at the same time). one of the following licenses is necessary:
     
    enclp epsxl etsxl cndc
     
     
    The following commands don't need any additional license but needs more computing time:
     
    set_analysis_view -setup {func_min } -hold {func_min}
     
    timeDesign -signOff -expandedViews -timingDebugReport -outDir REPORTS
    timeDesign -signOff -expandedViews -timingDebugReport -hold -outDir REPORTS
     
    write_sdf -version 3.0 -prec 3 -edges check_edge -force_calculation -view func_min -typ_view func_min ies2_digital_v1_min.sdf
     
    set_analysis_view -setup {func_typ } -hold {func_typ }
     
    timeDesign -signOff -expandedViews -timingDebugReport -outDir REPORTS
    timeDesign -signOff -expandedViews -timingDebugReport -hold -outDir REPORTS
     
    write_sdf -version 3.0 -prec 3 -edges check_edge -force_calculation -view func_typ -typ_view func_typ ies2_digital_v1_typ.sdf
     
    set_analysis_view -setup {func_max } -hold {func_max}
     
    timeDesign -signOff -expandedViews -timingDebugReport -outDir REPORTS
    timeDesign -signOff -expandedViews -timingDebugReport -hold -outDir REPORTS
     
    write_sdf -version 3.0 -prec 3 -edges check_edge -force_calculation -view func_max -typ_view func_max ies2_digital_v1_max.sdf
     
    It should be avoided to use
     
    set_analysis_view -setup {func_max } -hold {func_min}
     
    to create the SDFs, because SDF is not written completely. Max SDF will not include HOLD checks and min SDF will not have SETUP checks.

    New placement and routing options for 3-metal designs

    EDI10.1 provides some options to improve placement and routing in 3-metal processes.

      Placement:
        setPlaceMode -threeLayerMode 1 -wireLenOptEffort high
        placeDesign

      Routing (NanoRoute):
        setNanoRouteMode -routeExpCongestionMode true
        routeDesign

     

    Optimizing Clock Trees for Power

    There are some options that should help to optimize the power for clock trees. In the clock tree specification file you can set the option:

     AutoCTSRootPin clk
    Period 200ns
    MaxDelay 20ns # set_clock_latency
    ...
    PadBufAfterGate YES
    ...
    This will place buffers AFTER Gating components. In the command line set:
    encounter>setCTSMode -powerAware true

    With this option, CTS will try to optimize power consumption and will also give power reports at the end.


    Timing DRV Correction for selected nets

    The timing design rules (load-limit, slew-limit) can be corrected for selected nets only by executing the command:

    • optFanout -selNetFile <File with Netnames>

    The file ist just a list of netnames (one in each line). The command 'report_net -pin' can be used to find the name of a net when the instance name and the pin is known. For example

    • report_net -pin i1/u3/A

    reports the net that is connected to pin A of instance i1/u3.

    Avoid modifying of instances during optimization

    Sometimes instances should not be modified during optimization steps in encounter. For example if a delay cell was inserted on purpose the optimization should not delete it. This can be achieved by adding following statement to the constraints:

      set_dont_touch <instance name>

    The statement can also be used to stop encounter modifing a complete hierarchical instance not only a single cell. Encounter will not insert or modify any cell in this module.


    Additional I/O Pins

    How to get an additional pin to an existing one to have an I/O pin for the same net on different places.

    There is no menu command or text command to do that. You can just do it by modifying a DEF or Floorplan-File in the following way (DEF shown):

    PINS 2 ;
    - netout + NET netout + DIRECTION INPUT + USE SIGNAL
    + LAYER Metal2 ( -280 0 ) ( 280 560 )
    + FIXED ( 23100 60000 ) S ;
    - netout.extra1 + NET netout + DIRECTION INPUT + USE SIGNAL
    + LAYER Metal2 ( -280 0 ) ( 280 560 )
    + FIXED ( 24100 60000 ) S ;
    END PINS

    If bus pins have to be doubled the syntax is the following (the extra1 extension has to be added before the bus number):

    PINS 2 ;
    - netout<0> + NET netout + DIRECTION INPUT + USE SIGNAL
    + LAYER Metal2 ( -280 0 ) ( 280 560 )
    + FIXED ( 23100 60000 ) S ;
    - netout.extra1<0> + NET netout + DIRECTION INPUT + USE SIGNAL
    + LAYER Metal2 ( -280 0 ) ( 280 560 )
    + FIXED ( 24100 60000 ) S ;
    END PINS

    Read in the modified DEF and you will see the additional pin.