Assura Design Rule Check

 

The rule file for DRC enables online checking during the design phase and final verification before tape-out.
For final verification you should note that the Standard Family Cells do not conform to the design rules and therefore should be excluded from the design rule check.
A simple method is to generate a level of hierarchy on top of the final layout which instantiates all cells from SFCLIB.

Assura DRC can be invoked from a Virtuoso Layout L/XL/GXL window through the menu:

Assura -> Run DRC...

The following form will pop up:

Check, that the Rules File and Technology are correctly specified (must correspond to your design technology!).

To set switches for DRC you have to push the "Set Switches" button, to get another form where you can select various switches:

Before submitting any data for fabrication, a DRC check must be run without any switches. During the design phase the following switches may be used:

csxswitch
Allows to switch off some checks and 'relax' some checks for technology C35 that would cause DRC errors in 'CSX' layouts which have been transformed to technology C35.

device_debug
Reports all recognized devices in the DRC results database.

gds2input
Has to be used if your input for Assura is a GDSII database. Therefore set:
  Layout Design Source => Stream
  Rule Set ==> gdsII

grid
Allows to check for offgrid structures. It is recommended to use a grid of 0.05µm for technologies C35, S35 and H35.
Normally grid violations are uncritical but could cause systematic mismatch when offgrid geometries are used for high precision analog elements.

no_antenna
Allows to switch off antenna checks.

no_coverage
This switch can be used to disable the checks for metal and poly coverage when performing DRC.

no_elements
Disables specific checks (element rules) for primitive devices.

no_erc
ERC is switched off (floating POLY1, floating POLY2, PSUB without TAP ...)

no_holes
Disables MetX-hole checks.

no_info
Disables all checks that are only for informational purpose (not included in the Design Rule Document)

no_recommendation
Disables all checks that consider recommendations.

 

Viewing DRC Errors

After performing a DRC, the reported DRC errors are shown in the Error Layer Window (menu: Assura -> Open ELW):

 

Assura Utilities

A number of Assura utilities is provided to generate required fill structures. These utilities described in the following section can be used on demand.
Do not use the LAYGEN utility anymore since the generation of additional required layers is done at ams automatically

To bring up the dialog box for the Assura utilities from the layout window select:

hitkit Utilities -> Assura Utilities


Be aware that the result library has to differ from your project library not to overwrite the original layout.
Currently the following utilities are available:

NOTCHFILL

Generates metal structures to fill metal notches (for example caused by Silicon Ensemble).

FILLMETTOP

Generates fixed size metal structures on your top level metal layer to avoid maximum top metal spacing errors.
Layer "NOFILL" may be used to avoid automatic generation of metal structures in a specified area

FILLPATTERN

Generates fixed size metal structures on all metal layers except top metal to reach the required metal densities.
Layer "NOFILL" may be used to avoid automatic generation of metal structures in a specified area